In recent years, electric devices, such as a computer and a printer, are connected and used with a network in many cases. In this case, a plurality of standards of the cable which connects the electric device and the network exist. On the other hand, the electric device which performs high-speed communication with the maximum clock frequency of 125 MHz is proposed. Therefore, when the transmission speed of the electric device and the cable standard are not in agreement, a timing adjustment of output data is needed. Corresponding to an input/output of DDR (Double Data Rate), the clock frequency needs to be changed to the frequency of 125 MHz, 25 MHz, or 2.5 MHz based on the standard of Gigabit Ethernet.
In relation to the timing adjustment technology of such output data, the transmitting control circuit with FIFO (First-In First-Out) buffer which buffers IP (Internet Protocol) packet is disclosed in Japanese Patent application Laid-Open No. 2009-188479. Then, the packet data generated by CPU (Central Processing Unit) is saved in the FIFO buffer synchronizing with a clock signal more nearly high-speed than standard clock signal RCK (for example, 125 MHz) corresponding to the transmission speed of the communications network. Moreover, the packet data saved in the FIFO buffer is read synchronizing with the standard clock signal RCK.
However, in Japanese Patent application Laid-Open No. 2009-188479, in order to perform a data processing efficiently, the output speed adjustment of the data outputted from the CPU is performed, but an input speed adjustment of the data inputted into the CPU is not performed. This reason is for improving the data processing efficiency, assuming that the transmission speed in the network is fixed speed. Therefore, since the timing adjustment of the output data cannot be performed when the transmission speed is not fixed speed, there is a possibility that the correct communication cannot be performed.